Minimum qualifications:
- Bachelor's degree in Electronic Engineering or Computer Engineering, or equivalent practical experience.
- Experience in Peripheral Component Interconnect Express (PCIe) validation and testing (e.g., compliance, system level debug).
- Experience in embedded C/C++ code development.
Preferred qualifications:
- Experience in PCIe compliance measurements using high-end equipment (e.g., Analyzer, Exerciser).
- Experience with development using pre-silicon tools (e.g., Field Programmable Gate Array (FPGA)/Emulator).
- Knowledge of Peripheral Component Interconnect Express (PCIe) domain.
- Knowledge of ARM based SoC architecture (e.g., Boot flow, High-speed I/F initialization).
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Work with teams on test definition, timing budget analysis and provide system level breakdown of timing budget (e.g., standalone, full system load).
- Support platform ramp in debugging, integration of new Peripheral Component Interconnect Express (PCIe) endpoints, and triage for PCIe related failures.
